SHADAN

College of Engineering & Technology

(An ISO 9001:2015 Certified Institution)

Estd: 1995 |Approved By AICTE | Affiliated to JNTUH | Permitted by Govt of T.S | I S O Certified Institution| Registered with NSS| Member of National Digital Library| Institutional Member of Oracle Academy | Member of NPTEL(SWAYAM), MHRD | Enrolled in J-HUB |Applied for 2f(UGC)|Participated in N I R F, MHRD | Enrolled in Unnat Bharat Abhiyan.
Department of Electronics & Communication Engineering
Infrastructure Facilities

 List of Electronics and Communication  Engineering Laboratories

 

Sl. No.

Name of the Laboratory

Year/Sem

1

ELECTRONIC DEVICES   AND CIRCUITS LAB

B.Tech II/I

2

DIGITAL SYSTEM   DESIGN LAB

B.Tech II/I

3

BASIC SIMULATION LAB

B.Tech II/I

4

ELECTRONIC CIRCUIT   ANALYSIS LAB

B.Tech II/II

5

IC APPLICATIONS LAB

B.Tech II/II

6

ANALOG AND DIGITAL   COMMUNICATIONS LAB

B.Tech II/II(Common to ME, Civil)

7

MICROPROCESSORS   & MICROCONTROLLERS LAB

B.Tech III/I ( Common ECE&EEE)

8

DATA COMMUNICATIONS   AND NETWORKS LAB

B.Tech III/I

9

DIGITAL SIGNAL   PROCESSING LAB

B.Tech III/II( Common ECE&EEE)

10

E – CAD LAB

B.Tech III/II

11

SCRIPTING LANGUAGES   LAB

B.Tech III/II

12

VLSI AND E-CAD LAB

B.Tech IV/I

13

MICROWAVE   ENGINEERING LAB

B.Tech IV/I

14

DIGITAL SYSTEM DESIGN AND VERIFICATION LAB

M.TECH VLSI- I/I

15

ANALOG AND DIGITAL CMOS LAB

M.TECH VLSI- I/II

16

VLSI DESIGN AND VERIFICATION LAB

M.TECH VLSI- I/II

17

MICROCONTROLLERS AND PROGRAMMABLE DIGITAL SYSTEM  PROCESSORS LAB

M.TECH ES- I/I

18

SYSTEM DESIGN WITH EMBEDDED LINUX LAB

M.TECH ES- I/I

19

RTL SIMULATION AND SYNTHESYS WITH PLDs LAB

M.TECH ES- I/II

20

ADVANCED DIGITAL SIGNAL PROCESSING LAB

M.TECH ES- I/II

 

1.ELECTRONICS DEVICE AND CIRCUITS LAB(II/I):

EQUIPMENT NAME

NO’s

LIST OF EXPERIMENTS

Regulated power supply (0-30v)

10

1. PN Junction diode characteristics A) Forward bias B) Reverse bias.

 2. Zener diode characteristics and Zener as voltage Regulator

3. Full Wave Rectifier with & without filters

 4. Input and output characteristics of BJT in CE Configuration

5. Input and output characteristics of FE in CS Configuration

6. Common Emitter Amplifier Characteristics

7. Common Base Amplifier Characteristics

8. Common Source amplifier Characteristics

 9. Measurement of h-parameters of transistor in CB, CE, CC configurations

10. Switching characteristics of a transistor

11. SCR Characteristics.

12. Types of Clippers at different reference voltages

 13. Types of Clampers at different reference voltages

14. The steady state output waveform of clampers for a square wave input

Multimeters

10

Voltmeters (0-50v)

3

Voltmeters (0-100v)

3

Ammeters (0-100uA)

2

Ammeters (0-10mA)

5

CRO’s (0-20MHtz) dual channel

10

Function Generators (0-1MHtz)

10

Decade Resistance Boxes

10

Decade Capacitance Boxes

8

Decade inductance Boxes

10

Ammeters (0-1mA)

5

Ammeters (0-200uA)

5

Bread Boards

15

Electronics Components as per the design of the  circuit – resistor ,capacitors, BJTs,SCRs,UJTs,FETs,Diodes(Si or Ge),Zener Diode

100


2.DIGITAL SYSTEM DESIGN LAB(II/I)

EQUIPMENT DETAIL

NO’s

LIST OF EXPERIMENTS

0-5v Regulated Power Supply

4

1. Realization of Boolean Expressions using Gates

2. Design and realization logic gates using universal gates 3. Generation of clock using NAND / NOR gates

 4. Design a 4 – bit Adder / Subtractor

5. Design and realization of a 4 – bit gray to Binary and Binary to Gray Converter

6. Design and realization of an 8 bit parallel load and serial out shift register using flip-flops.

 7. Design and realization of a Synchronous and Asynchronous counter using flip-flops

8. Design and realization of Asynchronous counters using flip-flops

 9. Design and realization of 8×1 MUX using 2×1 MUX

10. Design and realization of 4 bit comparator

11. Design and Realization of a sequence detector-a finite state machine

0-12V Regulated Power Supply

10

CROs(0-20hz)dual channel

10

Bread board/general purpose trainer kits

10

74xx digital ICS

50

Multimeter

8


3.BASIC SIMULATION LAB(II/I)

EQUIPMENT NAME

NO’s

LIST OF EXPERIMENTS

MAT LAB or Equivalent Software with os

35

1. Basic Operations on Matrices.

2. Generation of Various Signals and Sequences (Periodic and Aperiodic), such as Unit Impulse, Unit Step, Square, Saw tooth, Triangular, Sinusoidal, Ramp, Sinc.

3. Operations on Signals and Sequences such as Addition, Multiplication, Scaling, Shifting, Folding, Computation of Energy and Average Power.

 4. Finding the Even and Odd parts of Signal/Sequence and Real and Imaginary parts of Signal.

 5. Convolution for Signals and sequences.

 6. Auto Correlation and Cross Correlation for Signals and Sequences.

 7. Verification of Linearity and Time Invariance Properties of a given Continuous/Discrete System.

8. Computation of Unit sample, Unit step and Sinusoidal responses of the given LTI system and verifying its physical realiazability and stability properties.

9. Gibbs Phenomenon Simulation.

10. Finding the Fourier Transform of a given signal and plotting its magnitude and phase spectrum.

11. Waveform Synthesis using Laplace Transform.

12. Locating the Zeros and Poles and plotting the Pole-Zero maps in S-plane and Z-Plane for the given transfer function.

13. Generation of Gaussian noise ( Real and Complex), Computation of its mean, M.S. Value and its Skew, Kurtosis, and PSD, Probability Distribution Function.

14. Verification of Sampling Theorem.

15. Removal of noise by Autocorrelation / Cross correlation.

16. Extraction of Periodic Signal masked by noise using Correlation.

17. Verification of Weiner-Khinchine Relations. 18. Checking a Random Process for Stationarity in Wide sense.

Computer systems with latest specification

35


4.ELECTRONIC CIRCUIT ANALYSIS LAB(II-II)

EQUIPMENT NAME

NO’s

LIST OF EXPERIMENTS

Regulated power supply (0-30v)

10

1. Common Emitter Amplifier (*)

2. Two Stage RC Coupled Amplifier

3. Cascode amplifier Circuit (*)

 4. Darlington Pair Circuit

5. Current Shunt Feedback amplifier Circuit

6. Voltage Series Feedback amplifier Circuit (*)

 7. RC Phase shift Oscillator Circuit (*)

8. Hartley and Colpitt’s Oscillators Circuit

9. Class A power amplifier

10. Class B Complementary symmetry amplifier (*)

 11. Design a Monostable Multivibrator

12. The output voltage waveform of Miller Sweep Circuit

CRO’s (0-20MHtz) dual channel

10

Function Generators (0-1MHtz)

10

Bread Boards

15

Power Amplifier Kits(Class A,Class B,Complimentary symmetry kits)

2

Tuned Amplifier kits

2

Computer System with latest specification

35

Analog Circuit simulation software / p spice/ multisim/equivalent software

10

Heartley and Colpitts oscillators circuit kits

2

Millars sweep circuit kits

1

Components – resistor ,capacitors, BJTs,FETs,Diodes

100


5.IC Application Lab(II/I)

EQUIPMENT NAME

NO’s

LIST OF EXPERIMENTS

0-5v Regulated power supply

4

1. Inverting and Non-Inverting Amplifiers using Op Amps

 2. Adder and Subtractor using Op Amp.

3. Comparators using Op Amp.

4. Integrator Circuit using IC 741.

5. Differentiator Circuit using Op Amp.

6. Active filter Applications-LPF, HPF (First Order)

7. IC 741 waveform Generators-Sine, Square wave and Triangular Waves.

8. Mono-Stable Multivibrator using IC 555.

9. Astable multivibrator using IC 555.

 10. Schmitt Trigger Circuits using IC 741.

11. IC 565-PLL Applications.

12. Voltage Regulator using IC 723

 13. Three terminal voltage regulators-7805, 7809, 7912

CRO’s (0-20MHtz) dual channel

10

Multimeter

8

741Op Amp IC, 555 lines IC,565 PLL IC

50

723 VOLTAGE REGULATED IC 7805-7912 ICs

20

Bread Board

10


6.ANALOG COMMUNICATION LAB(II/II)

EQUIPMENT NAME

NO’s

LIST OF EXPERIMENTS

CRO’s (0-20MHtz) dual channel

10

1. (i) Amplitude modulation and demodulation (ii) Spectrum analysis of AM

2. (i) Frequency modulation and demodulation (ii) Spectrum analysis of FM

 3. DSB-SC Modulator & Detector

 4. SSB-SC Modulator & Detector (Phase Shift Method)

 5. Frequency Division Multiplexing & De multiplexing

6. Pulse Amplitude Modulation & Demodulation

7. Pulse Width Modulation & Demodulation

8. Pulse Position Modulation & Demodulation

 9. PCM Generation and Detection

10. Delta Modulation

11. Frequency Shift Keying: Generation and Detection

12. Binary Phase Shift Keying: Generation and Detection 13. Generation and Detection (i) DPSK (ii) QPSK

Function generator(0-2mhz)

10

Spectrum Analyser 3mhz

2

Regulated power supply(0-30v)

13

Amplitude modulation and demodulatiom kits

3

Frequency modulation & demodulation

8

DSB-SC modulation & demodulation

4

SSB-SC modulation & demodulation

5

 Frequency devision multiplxing kits and Demultiplexing kits

1

Pulse width Modulation and demodulation kit

8

Pulse Position Modulation and demodulation kit

5

PCM Generation and Detection kit

4

Delta modulation kit

4

FSK Generation and Detection kit

2

BPSK Generation and Detection kit

1

DPSK Generation and Detection kit

4

QPSK Generation and Detection kit

1 


 
  7.MICROPROCESSORS AND MICROCONTROLLERS LAB (B.Tech III/I (ECE))

EQUIPMENT NAME

NO’s

LIST OF EXPERIMENTS

 

8086 kit

9

 

1.    Assembly Language Programs to 8086 to Perform

2.    Arithmetic, Logical, String Operations on 16 Bit and 32-Bit Data.

3.    Bit level Logical Operations, Rotate, Shift, Swap and Branch operations.

4.    Assembly Language Programs to Perform Arithmetic

1.      (Both Signed and Unsigned) 16 Bit

5.    Data Operations, Logical Operations (Byte and Bit Level Operations), Rotate, Shift, Swap and Branch Instructions

6.    Time delay Generation Using Timers of 8051.

7.    Serial Communication from / to 8051 to / from I/O devices.

8.    Program Using Interrupts to Generate Square Wave 10 KHZ Frequency        on P2.1 Using Timer 0 8051 in 8 bit Auto reload Mode and Connect a 1 HZ Pulse to INT1 pin and Display on Port 0. Assume Crystal Frequency as 11.0592 MHZ

9.    7 Segment Display to 8051.

10.  Matrix Keypad to 8051.

11.  Sequence Generator Using Serial Interface in 8051.

12.  8 bit ADC Interface to 8051.

13. Triangular Wave Generator through DAC interfaces to 8051.

 

8051kit

4

Interfacing 7 Segment Display to 8051

 

3

Interfacing Matrix Keypad to 8051

2

 

8 bit ADC Interface to 8051

 

3

 

DAC interfaces to 8051

2

 

CRO’s 0-20MHz

1

 

  1. DATA COMMUNICATIONS AND NETWORKS LAB (B.Tech III/I (ECE))

EQUIPMENT NAME

NOS

 

LIST OF EXPERIMENTS

 

Computer System with Latest

 Configuration

30

 

1.      Writing a TCL Script to create two nodes and links between nodes

2.      Writing a TCL Script to transmit data between nodes

3.      Evaluate the performance of various LAN Topologies

4.      Evaluate the performance of Drop Tail and RED queue management schemes

5.      Evaluate the performance of CBQ and FQ Scheduling Mechanisms

6.      Evaluate the performance of TCP and UDP Protocols

7.      Evaluate the performance of TCP, New Reno and Vegas

8.      Evaluate the performance of AODV and DSR routing protocols

9.      Evaluate the performance of AODV and DSDV routing protocols

10.  Evaluate the performance of IEEE 802.11 and IEEE 802.15.4

11.  Evaluate the performance of IEEE 802.11 and SMAC

12.  Capturing and Analysis of TCP and IP Packets

13.  Simulation and Analysis of ICMP and IGMP Packets

14.  Analyze the Protocols SCTP, ARP, NetBIOS, IPX VINES

15. Analysis of HTTP, DNS and DHCP Protocols

Open Source software like NS-2,

 NSG-2.1 and Wire SHARK

30


 9.DIGITAL SIGNAL PROCESSING LAB
(B. Tech III/II (ECE))

EQUIPMENT NAME

NOS.

LIST OF EXPERIMENTS

Computers

35

1.      Generation of Sinusoidal Waveform / Signal based on Recursive Difference Equations

2.      Histogram of White Gaussian Noise and Uniformly Distributed Noise.

3.      To find DFT / IDFT of given DT Signal

4.      To find Frequency Response of a given System given in Transfer Function/ Differential equation

5.      form.

6.      Obtain Fourier series coefficients by formula and using FET and compare for half sine wave.

7.      Implementation of FFT of given Sequence

8.      Determination of Power Spectrum of a given Signal(s).

9.      Implementation of LP FIR Filter for a given Sequence/Signal.

10.  Implementation of HP IIR Filter for a given Sequence/Signal

11.  Generation of Narrow Band Signal through Filtering

12.  Generation of DTMF Signals

13.  Implementation of Decimation Process

14.  Implementation of Interpolation Process

15.  Implementation of I/D Sampling Rate Converters

16. Impulse Response of First order and Second Order Systems.

   MATLAB / Lab View /

Equivalent

35

CRO’s 0-20 MHz

5

Function Generator 0-1 MHz

5

 CCS Studio / Equivalent  Processors Simulation

35

DSP processors (TI / Analog Devices / Equivalent)

5

 

  1. e – CAD LAB (B. Tech III/II)

EQUIPMENT NAME

 

NO’S

 

LIST OF EXPERIMENTS

Xilinx / Altera / Any Equivalet FPGA’s Board, Zed / Zynq Boards

2

1.      Realize all the logic gates

2.      Design of 8-to-3 encoder (without and with priority) and 2-to-4 decoder

3.      Design of 8-to-1 multiplexer and 1-to-8 demultiplexer

4.      Design of 4 bit binary to gray code converter

5.      Design of 4 bit comparator

6.      Design of Full adder using 3 modeling styles

7.      Design of flip flops: SR, D, JK, T

8.      Design of 4-bit binary, BCD counters (synchronous/ asynchronous reset) or any sequence

9.      counter

10.  Finite State Machine Design

11.  Layout, physical verification, placement & route for complex design, static timing analysis, IR

12.  drop analysis and crosstalk analysis for the following:

Ø  Basic logic gates

Ø  CMOS inverter

Ø  CMOS NOR/ NAND gates

Ø  CMOS XOR and MUX gates

Ø  Static / Dynamic logic circuit (register cell)

Ø  Latch

Ø  Pass transistor

13.  Layout of any combinational circuit (complex CMOS logic gate).

Xilinx / Vivado Software Licences

30

 

11.SCRIPTING LANGUAGES LAB (B. Tech III/II)

EQUIPMENT NAME

QUANTITY

 

LIST OF EXPERIMENTS

Computer System with Linux OS and Ruby, TCL, PERL Installed

60

 

1.      Write a Ruby script to create a new string which is n copies of a given string where n is a nonnegative integer

2.      Write a Ruby script which accept the radius of a circle from the user and compute the parameter

and area.

3.      Write a Ruby script which accept the user’s first and last name and print them in reverse order

with a space between them

4.      Write a Ruby script to accept a filename from the user print the extension of that

5.      Write a Ruby script to find the greatest of three numbers

6.      Write a Ruby script to print odd numbers from 10 to 1

7.      Write a Ruby scirpt to check two integers and return true if one of them is 20 otherwise return

8.      their sum

9.      Write a Ruby script to check two temperatures and return true if one is less than 0 and the other

10.  is greater than 100

11.  Write a Ruby script to print the elements of a given array

12.  Write a Ruby program to retrieve the total marks where subject name and marks of a student

13.  stored in a hash

14.  Write a TCL script to find the factorial of a number

15.  Write a TCL script that multiplies the numbers from 1 to 10

16.  Write a TCL script for Sorting a list using a comparison function

17.  Write a TCL script to (i)create a list (ii )append elements to the list (iii)Traverse the list

(iv)Concatenate the list

18.  Write a TCL script to comparing the file modified times.

19.  Write a TCL script to Copy a file and translate to native format.

a) Write a Perl script to find the largest number among three numbers.

b) Write a Perl script to print the multiplication tables from 1-10 using subroutines.

20.  Write a Perl program to implement the following list of manipulating functions

a)Shift

b)Unshift

c) Push

a) Write a Perl script to substitute a word, with another word in a string.

b) Write a Perl script to validate IP address and email address.

              21. Write a Perl script to print the file in reverse         order using command line arguments

 

12.VLSI AND E-CAD LAB(B.TECH   IV/I)

EQUIPMENT NAME

NO’s

LIST OF EXPERIMENTS

Computers with OS Latest specification

30

E-CAD programs:

1. HDL code to realize all the logic gates

2. Design of 2-to-4 decoder

 3. Design of 8-to-3 encoder (without and with priority)

4. Design of 8-to-1 multiplexer and 1-to-8 demultiplexer

 5. Design of 4 bit binary to gray code converter

6. Design of 4 bit comparator

 7. Design of Full adder using 3 modeling styles

 8. Design of flip flops: SR, D, JK, T

9. Design of 4-bit binary, BCD counters ( synchronous/ asynchronous reset) or any sequence counter

10. Finite State Machine Design

VLSI programs

1. Basic logic gates

2. CMOS inverter

3. CMOS NOR/ NAND gates

4. CMOS XOR and MUX gates

5. Static / Dynamic logic circuit (register cell)

6. Latch

7. Pass transistor

8. Layout of any combinational circuit (complex CMOS logic gate).

9. Analog Circuit simulation (AC analysis) – CS & CD amplifier

Xilinx or equivalent CAD simulation tool chain for VHDL/verilog Design(licenced)

30

CMOS designing  using tools like cadence/synopsis/mwntal graphics/equilent(licenced)

30

Xilinx /altera/any equilent FPGAS

2

Pattern generator &logic analyzer of 32 channel or bit generator and logic analyzer

1

 

  1. MICROWAVE ENGINEERING LAB (IV/I)

EQUIPMENT NAME

NO’s

LIST OF EXPERIMENT

Klystron /gunn diode based microwave bench setup including corresponding power supply

4

1. Reflex Klystron Characteristics

2. Gunn Diode Characteristics

3. Directional Coupler Characteristics

 4. VSWR Measurement of Mached load4

 5. VSWR mesurement of with open and short circuit loads

 6. Measurement of Waveguide Parameters

7. Measurement of Impedance of a given Load

8. Measurement of Scattering Parameters of a E plane Tee

9. Measurement of Scattering Parameters of a H plane Tee

 10. Measurement of Scattering Parameters of a Magic Tee

11. Measurement of Scattering Parameters of a Circulator 12. Attenuation Measurement

13. Microwave Frequency Measurement

14. Antenna Pattern Measurements.

Gunn diode based micro wave bench setup including gunn power supply

1

Micro Ammeter(0-500uA)

5

VSWR Meter

9

Micro wave components

50

a)slotted section

9

b)magic T junction

5

c)circulator

6

d)directional coupler for 2 directivities

3

e)attenuators for 2 different attenuators

6

f)Matched termination

15

E-Plane T junction

2

H-Plane T junction

2

Pin detector mounts

6


PG LABS

PG VLSISYSTEM DESIGN  LABS:

  1. DIGITAL DESIGN AND VERIFICATION LAB(I/I)

EQUIPMENT NAME

NO’s

LIST OF EXPERIMENTS

Verilog Hdl/Xilinx/Vivado/Equivalent Software

20

1. 8:1 Mux/Demux, Full Adder, 8-bit Magnitude comparator, Encoder/decoder, Priority encoder, Parity generator

 2. Code converters

3. D-FF, 4-bit Shift registers (SISO, SIPO, PISO, bidirectional), 3-bit Synchronous Counters.

 4. Sequence generator/detectors, Synchronous FSM – Mealy and Moore machines.

 5. Vending machines – Traffic Light controller, ATM, elevator control.

6. PCI Bus &Arbiter.

7. Single and Dual port SRAM

8. Arithmetic circuits like serial adder/ subtractor, parallel adder/subtractor, serial/parallel multiplier.

VLSI front end and back end tools(cadence/mentor Graphics)Xilinx/synopsis equivalent

20

Computers with latest configuration

20

 

15.ANALOG AND DIGITAL CMOS VLSI DESIGN LAB(I/II)

EQUIPMENT NAME

NO’s

LIST OF EXPERIMENTS

Verilog Hdl/Xilinx/Vivado/Equivalent Software

20

1) Use VDD=1.8V for 0.18um CMOS process, VDD=1.3V for 0.13um CMOS Process and VDD=1V for 0.09um CMOS Process.

a) Plot ID vs. VGS at different drain voltages for NMOS, PMOS.

b) Plot ID vs. VGS at particular drain voltage (low) for NMOS, PMOS and determine Vt.

 c) Plot log ID vs. VGS at particular gate voltage (high) for NMOS, PMOS and determine IOFF and sub-threshold slope.

d) Plot ID vs. VDS at different gate voltages for NMOS, PMOS and determine Channel length modulation factor.

e) Extract Vth of NMOS/PMOS transistors (short channel and long channel). Use VDS = 30mV

To extract Vth use the following procedure. i. Plot gm vs VGS using NGSPICE and obtain peak gm point. ii. Plot y=ID/(gm)1/2 as a function of VGS using Ngspice. iii. Use Ngspice to plot tangent line passing through peak gm point in y (VGS) plane and determine Vth.

f) Plot ID vs. VDS at different drain voltages for NMOS, PMOS, plot DC load line and calculate gm, gds, gm/gds, and unity gain frequency. Tabulate your result according to technologies and comment on it.

2) Use VDD=1.8V for 0.18um CMOS process, VDD=1.2V for 0.13um CMOS Process and VDD=1V for 0.09um CMOS Process.

 a) Perform the following i. Plot VTC curve for CMOS inverter and thereon plot dVout vs. dVin and determine transition voltage and gain g. Calculate VIL, VIH, NMH, NML for the inverter. ii. Plot VTC for CMOS inverter with varying VDD. iii. Plot VTC for CMOS inverter with varying device ratio.

 b) Perform transient analysis of CMOS inverter with no load and with load and determine tpHL, tpLH, 20%-to-80% tr and 80%-to-20% tf. (use VPULSE = 2V, Cload = 50fF) c) Perform AC analysis of CMOS inverter with fanout 0 and fanout 1. (Use Cin= 0.012pF, Cload = 4pF, Rload = k)

3) Use Ngspice to build a three stage and five stage ring oscillator circuit in 0.18um and 0.13um technology and compare its frequencies and time period.

 4) Perform the following

a) Draw small signal voltage gain of the minimum-size inverter in 0.18um and 0.13um technology as a function of input DC voltage. Determine the small signal voltage gain at the switching point using Ngspice and compare the values for 0.18um and 0.13umprocess.

b) Consider a simple CS amplifier with active load, as explained in the lecture, with NMOS transistor MN as driver and PMOS transistor MP as load, in 0.18um technology. R19 M.Tech. VLSI/VLSI Design/VLSI System Design (W/L)MN=5, (W/L)MP=10 and L=0.5um for both transistors. i. Establish a test bench, as explained in the lecture, to achieve VDSQ=VDD/2. ii. Calculate input bias voltage if bias current=50uA. iii. Use Ngspice and obtain the bias current. Compare its value with 50uA. iv. Determine small signal voltage gain, -3dB BW and GBW of the amplifier using small signal analysis in Ngspice (consider 30fF load capacitance). v. Plot step response of the amplifier for input pulse amplitude of 0.1V. Derive time constant of the output and compare it with the time constant resulted from -3dB BW vi. Use Ngspice to determine input voltage range of the amplifier

5) Three OPAMP INA. Vdd=1.8V Vss=0V, CAD tool: Mentor Graphics DA. Note: Adjust accuracy options of the simulator (setup->options in GUI).Use proper values of resistors to get a three OPAMP INA with differential-mode voltage gain=10. Consider voltage gain=2 for the first stage and voltage gain=5 for the second stage. i. Draw the schematic of op-amp macro model. ii. Draw the schematic of INA. iii. Obtain parameters of the op-amp macro model such that a. low-frequency voltage gain = 5×104, b. unity gain BW (fu) = 500KHz, c. input capacitance=0.2pF, d. output resistance = , e. CMRR=120dB iv. Draw schematic diagram of CMRR simulation setup. v. Simulate CMRR of INA using AC analysis (it’s expected to be around 6dB below CMRR of OPAMP). vi. Plot CMRR of the INA versus resistor mismatches (for resistors of second stage only) changing from -5% to +5% (use AC analysis). Generate a separate plot for mismatch in each resistor pair. Explain how CMRR of OPAMP changes with resistor mismatches. vii. Repeat (iii) to (vi) by considering CMRR of all OPAMPs to be 90dB.

 6) Technology: UMC 0.18um, VDD=1.8V. Use MAGIC or Microwind.

a) Draw layout of a minimum size inverter in UMC 0.18um technology using MAGIC Station layout editor. Use that inverter as a cell and lay out three cascaded minimum-sized inverters. Use M1 as interconnect line between inverters.

b) Run DRC, LVS and RC extraction. Make sure there is no DRC error. Extract the netlist.

c) Use extracted netlist and obtain tPHLtPLH for the middle inverter using Eldo.

 d) Use interconnect length obtained and connect the second and third inverter. Extract the new netlist and obtain tPHL and tPLH of the middle inverter. Compare new values of delay times with corresponding values obtained in part ‘c’

VLSI front end and back end tools(cadence/mentor Graphics)Xilinx/synopsis equivalent

20

Computers with latest configuration

20

Spice tool like  NGSPICE or Equivalent

20

  

16.VLSI DESIGN & VERIFICATION LAB (I/II)

EQUIPMENT NAME

NO’s

LIST OF EXPERIMENTS

Verilog Hdl/Xilinx/Vivado/Equivalent Software

20

1. Connect two of such FIFOs having different clock rates. Design and test a 2 location 4-bit wide FIFO. Can you explain problems associated with such a setup?

2. Building and testing a parameterised multi-bit adder using control swap (Fredkin) gates as building blocks.

3. Example of some basic circuits, finite state machines (Moore/Mealy). Test and debug code for muxes, encoder/decoders, counters, memory access.

4. Serial port design and integration within a system. Test and debug the code for a UART module with a FIFO interface. Connect two UART modules and transmit/receive data between them.

 5. Introduction to synthesis. Run a program to blink an LED on the FPGA. Establish a serial communication between board and computer host.

6. Any of the above designs, implement the physical layout

VLSI front end and back end tools(cadence/mentor Graphics)Xilinx/synopsis equivalent

20

Computers with latest configuration

20

 

  1. MICROCONTROLLERS AND PROGRAMMABLE DIGITAL SYSTEM PROCESSORS LAB (COMMON TO VLSI I/I & ES I/I)

EQUIPMENT NAME

NOS.

LIST OF EXPERIMENTS

 

Coretex-M3 Control Board set with built in IDE

5

1.      Blink an LED with software delay, delay generated using the SysTicktimer.

2.      System clock real time alteration using the PLL modules.

3.      Control intensity of an LED using PWM implemented in software andhardware

4.      Control an LED using switch by polling method, by interrupt method and flash the LED once.

5.      Take analog readings on rotation of rotary potentiometer connected to anADC channel.

6.      Temperature indication on an RGB LED.

7.      Evaluate the various sleep modes by putting core in sleep and deep sleepmodes.

8.      System reset using watchdog timer in case something goes wrong.

9.      Write a program to interface ADC and DAC with PSOC

10.  To develop an assembly code and C code to compute Euclidian distancebetween any two points.

11.  To develop assembly and C code for implementation of convolutionoperation.

12.  To design and implement filters in C to enhance the features of giveninput sequence/signal

DSP C6713 evaluation kit

2

Computers

20

Arduino IDE

5

 

Code Composer Studio(CCS)

20

 

  1. SYSTEM DESIGN WITH EMBEDDED LINUX LAB (ECE MTECH ES I Year I Semester)

EQUIPMENT NAME

NOS.

LIST OF EXPERIMENTS

Raspbery Pi

5

1. Functional Testing Of Devices: Flashing the OS on to the device into a stable functional state by porting desktop environment with necessary packages.

2. Exporting Display On To Other Systems: Making use of available laptop/desktop displays as a display for the device using SSH client & X11 display server.

3. GPIO Programming: Programming of available GPIO pins of the corresponding device using native programming language. Interfacing of I/O devices like LED/Switch etc., and testing the functionality.

4. Interfacing Chronos eZ430: Chronos device is a programmable Texas instruments watch which can be used for multiple purposes like PPT control, Mouse operations etc., Exploit the features of the device by interfacing with devices.

5. ON/OFF Control Based On Light Intensity: Using the light sensors, monitor the surrounding light intensity & automatically turn ON/OFF the high intensity LED’s by taking some predefined threshold light intensity value.

6. Battery Voltage Range Indicator: Monitor the voltage level of the battery and indicating the same using multiple LED’s (for ex: for 3V battery and 3 led’s, turn on 3 LED’s for 2-3V, 2 LED’s for 1-2V, 1 led for 0.1-1V & turn off all for 0V)

7. Dice Game Simulation: Instead of using the conventional dice, generate a random value similar to dice value and display the same using a 16X2 LCD. A possible extension could be to provide the user with option of selecting single or double dice game.

8. Displaying RSS News Feed On Display Interface: Displaying the RSS news feed headlines on a LCD display connected to device. This can be adapted to other websites like twitter or other information websites. Python can be used to acquire data from the internet.

9. Porting Openwrt To the Device: Attempt to use the device while connecting to a Wifi network using a USB dongle and at the same time providing a wireless access point to the dongle.

10. Hosting a website on Board: Building and hosting a simple website(static/dynamic) on the device and make it accessible online. There is a need to install server (eg: Apache) and thereby host the website.

11. Webcam Server: Interfacing the regular USB webcam with the device and turn it into fully functional IP webcam & test the functionality.

12. FM Transmission: Transforming the device into a regular FM transmitter capable of transmitting audio at desired frequency (generally 88-108 Mhz)

Beagle Bone Black-Rev C set

1

Raspbian Operating System

20

Debian Operating System

120

COMPUTERS

20

 

  1. RTL SIMULATION AND SYNTHESYS WITH PLDs LAB (MTECH ES I Year II Semester)

EQUIPMENT DETAIL

NOS.

LIST OF EXPERIMENTS

Xilinx FPGA Spartan 3e-100 or 250/equivalent

2

E-CAD Programs:                                                                                       

1.      HDL Code to realize all the logic gates.                               

2.      Design  of 2-to-4 decoder

3.       Design  of 8-to-3 encoder (without and with priority)

4.      Design of 8-to-1 multiplexer

5.      Design of 4 bit Binary to Gray code converter

6.      Design of Multiplexer/ Demultiplexer , comparator

7.      Design of Full Adder using 3 modeling styles

8.      Design of Flip Flops: SR, D, JK,T( Asynchronous  Reset and Synchronous  Reset)

9.      Design of 4-bit binary, BCD Counters(Asyn  Reset and Syn  Reset) or any Sequence Counter

10.  Finite State Machine Design

VLSI Programs:

1.      Introduction to Lay out design rules

2.      Layout, Physical verification ,placement & route for complex design, state timing analysis

IR drop analysis and crosstalk analysis of the following:

·         Basic Logic Gates

·         CMOS Inverter

·         CMOS NOR/NAND gates

·         CMOS XOR and MUX gates

·         CMOS 1-bit full adder

·         Static/Dynamic logic circuit

·         latch

·         pass transistor

3.      layout of any combinational circuit

4.      introduction to SPICE simulation and coding of NMOS/CMOS circuit

5.      SPICE simulation of basic analog circuits: Inverter /Differential Amplifier

6.      Analog Circuits simulation(AC Analysis)-CS & CD Amplifier

7.      System Level Design using PLL

 

ZedBoard ( Zynq-7000 XC7Z2020/ Equivalent

1

Computers

20

XilinixVivado 2017.3/ Equivalent

20

 

 

 

  1. ADVANCED DIGITAL SIGNAL PROCESSING LAB (ECE M.TECH ES- I YEAR II SEMESTER)

EQUIPMENT DETAIL

NOS.

LIST OF EXPERIMENTS

 

MATLAB/Equivalent

20

1.      GENERATIONOF BASIC SIGNALS(Unit Impulse, Exponential,  Unit Step,Ramp )

2.      GENERATIONOF BASIC SIGNALS( Sinusoidalsignal )

3.      FINDING THE FFT OF DIFFERENT SIGNALS

4.      PROGRAM TO VERIFY DECIMATION AND INTERPOLATION

5.      PROGRAM TO CONVERT CD DATA INTO DVD DATA

6.      Generation   Of   Dual   Tone   Multiple

            Frequency (DTMF) Signals

7.      POWER SPECTRAL DENSITY USING SQUARE MAGNITUDE AND     AUTOCORRELATION

8.      POWER SPECTRAL DENSITY USING PERIODOGRAM

9.      POWER SPECTRAL DENSITY ESTIMATION USING PERIODOGRAM AND MODIFEIED PERIODOGRAM

10.  POWER SPECTRAL DENSITY ESTIMATION USING BARLETT METHOD

11.  POWER SPECTRAL DENSITY ESTIMATION USING WELCH METHOD

12.  PSD ESTIMATION USING BLACKMAN AND TUKEY METHOD

13.  POWER SPECTRUM ESTIMATION USING YULE-WALKER  METHOD(PARAMETRIC METHOD)

14.  POWER SPECTRUM ESTIMATION USING BURG METHOD(PARAMETRIC METHOD)

 

 

Computers

20